1. Field of the Invention
This invention relates to a gate structure and, more particularly, to a T-shaped gate structure with high stem and low parasitic.
2. Description of the Prior Art
In circuits for high frequency applications, the unwanted series resistance and capacitance across the input terminals of a device must be reduced. To reduce the series resistance, the cross section of the gate metal should be maintained even when its length is reduced for short channel devices. To reduce the capacitance, the lateral areas of the gate electrode facing the source and drain should be minimized. This is achieved by adopting a two sections gate electrode structure 1 as depicted in FIG. 1, which shows a simplified schematic diagram of a high electron mobility transistor (HEMI) 1 having a substrate 11, a channel layer 12, a source 13, a drain 14 and a gate 15. The gate 15 has a head portion 151 and a stem portion 152, the dimension of the stem portion of the gate contacting the channel layer is defined as the gate length or channel length L2 which is made close to 100 nm in prior art for achieving high frequency performance. Whereas the head portion length L1 is made substantially larger than the gate length L2 to reduce the resistance of the gate in the direction of perpendicular to the direction of channel length and parallel to the surface of the substrate. Such a gate with the head portion substantially longer than that of the stem portion is often called a T-gate.
In addition to the abovementioned HEMT, which is a variant of gallium arsenide field effect transistor technology and where input signals are applied between the gate and source, such the T-gates also have been advantageously applied to metal semiconductor field effect transistors (“MESFETs”) and both of the above two are mainly used in satellite broadcasting receivers, high speed logic circuits and power modules. The narrow base of a T-gate structure provides a short channel length which results in increased speed and decreased power consumption. Parasitic resistances and capacitances that limit device speed are also reduced. The top portion of a T-gate is made wide so that the conductance of the T-gate remains high, for example, for high switching speeds.
In general, an Electron-beam (“E-beam”) lithography method is the most commonly used to fabricate a T-gate and does not limit to use a double or triple photoresist layer. FIG. 2A, FIG. 2B, FIG. 2C to FIG. 2D are diagrams showing a conventional process for forming a T-gate using e-beam. Typically, from FIG. 2A shown, substrate 21 is coated with a layer of first poly(methyl methacrylate)-based photoresist 22, a layer of second poly(methyl methacrylate)-based photoresist 23, and a layer of third poly(methyl methacrylate)-based photoresist 24. As shown in FIG. 2B, Photoresist layers 22 to 24 are then exposed to e-beam and developed to provide a patterned photoresist stack having generally T-shaped profile 25. FIG. 2C shows a layer of a conductive material 26 is then deposited on the entire surface inclusive of the surface of substrate 21 exposed by the patterning of the photoresist layers. Photoresist layers 22 to 24 are then removed, lifting-off the conductive material layer on the surface of photoresist layer 24 in the process, to provide T-gate structure 27 on substrate 21 as shown in FIG. 2D.
Accordingly, the thin photoresist will be used for small gate length to obtain fine pattern so that a T-gate with low stem is obtained. In addition, a complete gate technique, such as a sub-50 nm two-step recess, is performed to avoid the T-gate from collapsing and further to obtain high performance transistor. However, the abovementioned method is too complete for mass production and also limits the applications in sub-millimeter wave or THz monolithic microwave integrated circuit (MMIC).